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hi-8425, hi-8426 8-channel, ground /open, or supply / open sensor 4-channel 200 ma ground / open driver general description features the hi-8425 is a combined 8-channel discrete-to-digital sensor and quad low side driver fabricated with silicon-on- insulator (soi) technology for robust latch-up free operation. sense detection can either be gnd/open or supply/open as configured by the snse_sel pin. supply/open sensing is also referred to as 28v/open sensing. the sensing circuit window comparator thresholds can be fixed at the internal programmed values or can be set externally at the hi_set and lo_set pins, as selected by the pin. the digital sense outputs can be tri- stated by taking the pin high. the hi-8425 also offers four low side switches each capable of sinking 200 ma of current. each switch transistor is controlled by its own digital input pin and is fully fault protected. over-current conditions, such as a short circuit, are detected and inhibited while signaling the fault condition at the corresponding logic output. these four fault outputs are also available in a combined or output. the outputs are fully protected from transients when driving relays. the hi-8426 puts all of the features of the hi-8425 except the individual fault detection outputs, tri-state pin selection and fixed internal thresholds into a 32-pin chip scale package (qfn) which measures only 5mm x 5mm. interface to the digital subsystem is simple cmos logic inputs and outputs. the logic pins are compatible with 5v or 3.3v logic allowing direct connection to a wide range of microcontrollers or fpgas. ths_sel oe all sense inputs are internally lightning protected to do160g, section 22, cat az, bz and zz without external components. robust cmos silicon-on-insulator (soi) technology 8-channel selectable sense operation, gnd/open or supply/open selectable thresholds and hysteresis sense detection range 3v to 22v logic operation from 3.0v to 5.5v lightning protected sense inputs august 2013 32 - vwet 31 - vlogic 30 - hi_set 29 - lo_set 28 - snse_sel 27 - dsel_0 26 - dsel_1 25 - dsel_2 sense0 - 1 1-2 2-3 3-4 4-5 5-6 6-7 7-8 sense sense sense sense sense sense sense 24 - dsel_3 23-drv0 22-drv1 21 - gnd 20 - drv_2 19 - drv_3 18 - fault_or 17 - gnd so_0 - 9 so_1 - 10 so_2 - 11 so_3 - 12 so_4 - 13 so_5 - 14 so_6 - 15 so_7 - 16 hi-8426pci hi-8426pct 32 pin plastic 5mm x 5mm chip-scale package (qfn) (see page 15 for leaded qfp package options) pin configurations so_0 - 1 1 so_1 - 12 so_2 - 13 so_3 - 14 so_4 - 15 so_5 - 16 so_6 - 17 so_7 - 18 gnd-19 -20 40 - vlogic 39 - 38 - hi_set 37 - lo_set 36 - snse_sel 35 - fault_or 34 - dsel_0 33 - dsel_1 32 - dsel_2 31 - dsel_3 ths_sel vwet - 1 sense0 - 2 sense1 - 3 sense2 - 4 sense3 - 5 sense4 - 6 sense5 - 7 sense6 - 8 sense7 - 9 -10 oe 30 - 29 - fault_0 28 - drv_0 27 - drv_1 26 - fault_1 25 - gnd 24 - fault_2 23 - drv_2 22 - drv_3 21 - fault_3 HI-8425PCI hi-8425pct 40 pin plastic 6mm x 6mm chip-scale package (qfn) applications airbus abd0100h compliant 4 low-side 200 ma drivers 4.5 ohm on resistance over-current fault detection signaled by logic output max power dissipation automatically limited by fault protection diode clamps for discharging inductive loads holt integrated circuits (ds8425 rev. c) 08/13 www.holtic.com avionics discrete to digital sensing relay driver lamp driver discrete signaling
block diagram holt integrated circuits 2 voltage reference ths_sel vref_hi vlogic snse_sel hi_set lo_set vref_lo vwet v logic figure 2 vthi/10 vtlo/10 sense_0 sense_1 sense_2 sense_3 sense_4 sense_5 sense_6 sense_7 + - 360k 40k snse_sel snse_sel lightning protection so_0 so_1 so_2 so_3 so_4 so_5 so_6 so_7 v logic v wet + - 23.8k 3.3k 29k oe drive control current sense dsel_0 dsel_1 dsel_2 dsel_3 drv_0 fault_or gnd gnd drv_1 drv_2 drv_3 fault_0 fault_1 fault_2 fault_3 hi-8425, hi-8426
holt integrated circuits 3 symbol function description vwet supply optional input to supply relay wetting current to sense lines in gnd/open operation 50k to gnd sense0 discrete input discrete input 0. if snse_sel = 0 pin senses gnd/open. if snse_sel = 1, senses supply/open so_1 so_2 so_3 s s s s sense1 discrete input discrete input 1. if snse_sel = 0 pin senses gnd/open. if snse_sel = 1, senses supply/open sense2 discrete input discrete input 2. if snse_sel = 0 pin senses gnd/open. if snse_sel = 1, senses supply/open sense3 discrete input discrete input 3. if snse_sel = 0 pin senses gnd/open. if snse_sel = 1, senses supply/open sense4 discrete input discrete input 4. if snse_sel = 0 pin senses gnd/open. if snse_sel = 1, senses supply/open sense5 discrete input discrete input 5. if snse_sel = 0 pin senses gnd/open. if snse_sel = 1, senses supply/open sense6 discrete input discrete input 6. if snse_sel = 0 pin senses gnd/open. if snse_sel = 1, senses supply/open sense7 discrete input discrete input 7. if snse_sel = 0 pin senses gnd/open. if snse_sel = 1, senses supply/open digital input if high, so_n and fault outputs are high-impedance. has internal 30k pull-down resistor so_0 digital output high if snse_sel=0 and sense0 < or low if snse_sel=1 and sense0 > digital output digital output digital output o_4 digital output o_5 digital output o_6 digital output o_7 digital output fault_3 digital output high if driver 3 is attempting to sink excess current drv_3 switch output drain node of ground switch driver 3 gnd supply ground for logic and drv_2 drv_1 drv_0 dsel_3 digital input when high, turns on driver 3. dsel_3 has an internal 30k pull-down resistor vlogic supply logic supply. (3.0v - 5.5v) oe oe v, v high if snse_sel=0 and sense1 < v , or low if snse_sel=1 and sense1 > v high if snse_sel=0 and sense2 < v , or low if snse_sel=1 and sense2 > v high if snse_sel=0 and sense3 < v , or low if snse_sel=1 and sense3 > v high if snse_sel=0 and sense4 < v , or low if snse_sel=1 and sense4 > v high if snse_sel=0 and sense5 < v , or low if snse_sel=1 and sense5 > v high if snse_sel=0 and sense6 < v , or low if snse_sel=1 and sense6 > v high if snse_sel=0 and sense7 < v , or low if snse_sel=1 and sense7 > v analog ground return for drv0-3. gnd pin and the isolated backside pad should be grounded for optimum performance and power dissipation. switch output drain node of ground switch driver 2 fault_2 digital output high if driver 2 is attempting to sink excess current fault_1 digital output high if driver 1 is attempting to sink excess current switch output drain node of ground switch driver 1 switch output drain node of ground switch driver 0 fault_0 digital output high if driver 0 is attempting to sink excess current dsel_2 digital input when high, turns on driver 2. dsel_2 has an internal 30k pull-down resistor dsel_1 digital input when high, turns on driver 1. dsel_1 has an internal 30k pull-down resistor dsel_0 digital input when high, turns on driver 0. dsel_0 has an internal 30k pull-down resistor fault_or digital output high if any driver is attempting to sink excess current snse_sel digital input if low, sense pins are sensing open/gnd. if high, sense pins sense supply/open lo_set analog input if is high, this pin sets the lower window comparator threshold hi_set analog input if is high, this pin sets the upper window comparator threshold digital input if is low, comparator thresholds are set internally. has an internal 30k pull-up lo hi lo hi lo hi lo hi lo hi lo hi lo hi lo hi ths_sel ths_sel ths_sel ths_sel ths_sel pin descriptions hi-8425, hi-8426
functional description holt integrated circuits 4 sensing the 8 sense channels can be configured to meet the requirements of a variety of conditions and applications. table 1 summarizes basic function selection and table 2 gives more details on possible threshold values. for gnd/open sensing, the sns_sel pin is connected to gnd referring to the block diagram, figure 2, this selection will connect a 3.3k pull-up resistor through a diode to vlogic and a 23.8k resistor through 3 diodes to vwet. these resistors give extra noise immunity for detecting the open state while providing relay wetting current. configuring hi-8425 (40 pin version) - threshold select the hi-8425 offers a choice between internally fixed thresholds or external thresholds provided by the user. gnd/open sensing . , hi_set/lo_sel and vwet as described below sets the window comparator thresholds, v and v , the open input voltage when open, and the input current. is equal to 10x the voltage on the hi_set pin. is equal to 10x the voltage on the lo_set pin. this mode allows the user complete flexibility to define the thresholds and hysteresis levels. for applications that can take advantage of the very small 32 pin chip scale package of the hi-8426, is not available and an internal pull-up makes it mandatory to supply hi_set and lo_set externally. for correct operation, the v when open, must be higher than so so_n will be low. this condition requires vwet to be set greater than (vthi/0.9 + 2.25v) he standard open signal as characterized by a resistance of 100k or more with respect to signal common. the user should consider this 100k to ground case when setting the thresholds. ths_sel ths_sel thi tlo thi thlo thi tlo sense_n thi with set to gnd, the window comparator thresholds are fixed based on an internal reference. the high threshold, v , and the low threshold, v levels may be found in table 2. when the internal references are used the hi_set and lo_set pins should be connected to gnd. for applications with either large gnd offsets or thresholds higher than vlogic - 0.75v, is set high and the thresholds are set externally, for example by a simple resistor divider off the vlogic supply. in this case v v v . various arinc standards such as arinc 763 define t ths_sel ths_sel hi-8426 (32 pin version) threshold select open input voltage wetting current threshold select wetting current for gnd/open applications with vwet open, the wetting current with the input voltage at gnd is simply (vlogic - 0.75)/3.3k. when applying a higher voltage at the vwet pin the wetting current is (vlogic - 0.75)/3.3k + (vwet - 4.2)/127k. additional wetting current can be achieved by placing an external resistor and a diode between vwet and the individual sense inputs. the 8 sense channels can be configured to sense supply/open by connecting the snse_sel pin to vlogic. refering to figure 2, a 32k resistor is switched in series to provide a pull down in addition to the 400k of the comparator input divider to gnd. similar to the gnd/open case configuring , hi_set/lo_sel and vwet as described below sets the window compara- tor thresholds, the open input voltage when open and the wetting current. the threshold selections are handled in the same way as stated above for the gnd/open case. for set low, the internal reference nominally sets the window comparator. see table 2 for the for set high, the final thresholds are 10x the voltage set on the hi_set and lo_set pins. the vwet pin must be left open in the supply/open sensing case. for the supply/open case the wetting current into the sense input is the current sunk by the effective 28k to gnd. for v = 28v, i is 1ma. see figure 12. supply/open sensing ths_sel ths_sel ths_sel v and v threshold levels. thi thlo sense_n wet sense_n snse_sel oe so_n open or > vthi l (gnd/open) l l < vtlo l (gnd/open) l h x l (gnd/open) h z open or < vtlo h (v+/open) l h > vthi h (v+/open) l l x h (v+/open) h z h = vlogic, l = gnd , z = hi-z , x = dont care, v+ = v see table 2 for values of vthi/vtlo supply table 1. function table hi-8425, hi-8426
over-current shutdown fault conditions maximum dc power dissipation per driver is approximately 0.5w at room temperature. conditions that would cause the power to exceed this amount will result in a shut down of the driver. over-current shutdown is initiated when the driver pin voltage is more than approximately 1.5v from gnd. however there is a delay of approximately 11sec before the shutdown actually occurs giving the driver an opportunity to charge capacitive loads and thereby avoid shutdown. similarly, if the driver is on and a high load is suddenly switched on, the over-current shutdown will be delayed in activation. note that even when the over-current fault condition is present, the driver pin is still sourcing a few milliamps. this low current condition continues until the input is taken low or the load is removed. each driver has a converter that translates an over-current detection into a logic high output at its fault output. the fault_or output goes high if one or more fault outputs are high. these outputs can be tri-stated by setting high. oe functional description holt integrated circuits 5 output enable output drivers the output enable pin, , available on the hi-8425, tri- states all sense outputs and low side driver fault outputs to allow connecting the tri-state outputs in parallel with other tri-stated chips. the pin has a pull-down and when left open will cause these digital outputs to be driven to their logic levels. if the pin is high, these digital outputs are high impedance. oe oe oe low side drivers both product versions offer four low side drivers. each driver (nmos switch) is capable of sinking a minimum of 200ma while exhibiting a r of 4.5 typical. each output has diode clamps for protection during inductive kick-back for relay applications. off-state leakage is typically less than 10na at room temperature. the inputs, dsel0 through dsel3, have internal pull-downs which hold off the drivers until logic highs are presented. on table 2. configuration options and allowed threshold values -55c to 125c. vlogic snse_ sel operation vwet pin ths_ sel threshold selected maximum hi_set (vthi = hi_setx10) minimum lo_set (vtlo = lo_setx10) guaranteed high threshold guaranteed low threshold 3.0v open gnd/open l l internal - - 2.5v 1.0v 3.6v open gnd/open l l internal - - 2.7v 1.0v 3.3v 28v gnd/open l l internal - - 2.55v 1.0v 3.0v 7v gnd/open l h external 0.4v (4.0v) 0.3v (3.0v) vthi + 0.5v vtlo - 0.5v 3.6v 7v gnd/open l h external 0.4v (4.0v) 0.3v (3.0v) vthi + 0.5v vtlo - 0.5v 3.0v to 3.6v 28v gnd/open l h external 2.2v (22v) 0.3v (3.0v) vthi + 0.5v vtlo - 0.5v 3.0v to 3.6v open v+/open h l internal - - 15.5v 11.0v 3.0v to 3.6v open v+/open h h exernal 2.2v (22v) 0.3v (3.0v) vthi + 0.5v vtlo - 0.5v 4.5v open gnd/open l l internal - - 3.25v 1.0v 5.5v open gnd/open l l internal - - 3.75v 1.0v 5.0v 28v gnd/open l l internal - - 3.5v 1.0v 4.5v 7v gnd/open l h external 0.4v (4.0v) 0.3v (3.0v) vthi + 0.5v vtlo - 0.5v 5.5v 7v gnd/open l h external 0.4v (4.0v) 0.3v (3.0v) vthi + 0.5v vtlo - 0.5v 4.5v to 5.5v 28v gnd/open l h external 2.2v (22v) 0.3v (3.0v) vthi + 0.5v vtlo - 0.5v 4.5v to 5.5v open v+/open h l internal - - 15.5v 11.0v 4.5v to 5.5v open v+/open h h external 2.2v (22v) 0.3v (3.0v) vthi + 0.5v vtlo - 0.5v note: vthi = sense pin high threshold (hi_set x 10), vtlo = sense pin low threshold (lo_set x 10) hi-8425, hi-8426
holt integrated circuits 6 functional description 0.0 0.3 0.5 0.8 1.0 voltage waveform 4 t2 t1 v(%) t1 = 6.4s +/-20% t2 = 69s +/-20% t 50% peak 0.0 0.3 0.5 0.8 1.0 current/voltage waveform 5a t2 t1 i/v (%) t1 = 40s +/-20% t2 = 120s +/-20% t 50% peak 0.0 0.3 0.5 0.8 1.0 current/voltage waveform 5b t2 t1 i/v (%) t1 = 50s +/-20% t2 = 500s +/-20% t 50% peak figure 3. lightning waveforms table 3. waveform peak amplitudes lightning protection all sense_n inputs are protected to rtca/do-160g, section 22, categories az and bz, waveforms 3, 4, 5a, with no external components. in addition, all inputs are also protected to zz, waveforms 3 and 5b, to provide more robustness in composite airframe applications. table 3 and figure 3 give values and waveforms. level waveforms 3/3 4/1 5a/5a voc (v) / isc (a) voc (v) / isc (a) voc (v) / isc (a) 2 250/10 125/25 125/125 z 500/20 300/60 300/300 3 600/24 300/60 300/300 5b/5b voc (v) / isc (a) 125/125 300/300 300/300 -1.0 -0.5 0.0 0.5 1.0 t voltage/current waveform 3 peak 50% v/i (%) 1us/div. hi-8425, hi-8426
holt integrated circuits 7 application examples figure 4 input sensing with internal thresholds for gnd/open snse_sel = gnd low to high threshold = 2.7v high to low threshold = 1.0v for 28v/open snse_sel = vlogic low to high threshold = 15.5v high to low threshold = 11.0v sense0 sense1 sense2 sense3 sense4 sense5 sense6 sense7 oe vwet vlogic = 3.3v snse_sel ths_sel hi-8425 open vlogic hi_set lo_set gnd from sensors gnd so_0 so_1 so_2 so_3 so_4 so_5 so_6 so_7 hi_set = 1.12v lo_set = 0.64v 68k 15k 20k open vlogic = 3.3v sense0 sense1 sense2 sense3 sense4 sense5 sense6 sense7 oe low to high threshold = 11.2v high to low threshold = 6.4v vwet snse_sel ths_sel hi-8425 vlogic hi_set lo_set from sensors gnd vlogic = 3.3v vlogic = 3.3v so_0 so_1 so_2 so_3 so_4 so_5 so_6 so_7 10f 10v 0.1f 10v 3.3f 10v gnd 3.3f 10v figure 5 input sensing, 28v/open, typical abd0100h thresholds hi-8425, hi-8426
holt integrated circuits 8 application examples figure 6 input sensing, gnd/open typical abd0100h thresholds, 1ma wetting current figure 7 lowside output driving relay figure 8 lowside output driving led figure 9 lowside output driving lamp figure 10 lowside output driving resistive load sense0 sense1 sense2 sense3 sense4 sense5 sense6 sense7 oe low to high threshold = 9.7v high to low threshold = 5.6v vwet snse_sel ths_sel hi-8425 vlogic hi_set lo_set from sensors vlogic = 3.3v gnd so_0 so_1 so_2 so_3 so_4 so_5 so_6 so_7 hi_set = 0.97v lo_set = 0.56v 75k 13k 18k 28v vlogic = 3.3v gnd 10f 10v 0.1f 10v 3.3f 10v gnd 3.3f 10v v+ load drive control current sense dsel_n gnd hi-8425 fault_n drv_n v+ drive control current sense dsel_n gnd hi-8425 fault_n drv_n v+ drive control current sense dsel_n gnd hi-8425 fault_n drv_n v+ drive control current sense dsel_n gnd hi-8425 fault_n drv_n hi-8425, hi-8426
holt integrated circuits 9 application examples figure 11 lowside output used for discrete signaling with three separate users figure 12 input current vs. input voltage hi-8425 sense_n hi-8430 sense_n hi-8425 sense_n v+ drive control current sense dsel_n gnd hi-8425 fault_n drv_n hi-8425, hi-8426
note: stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. these are stress ratings only. operation at the limits is not recommended. absolute maximum ratings recommended operating conditions holt integrated circuits 10 voltages referenced to ground supply voltage (vlogic) ......................... -0.3v to +7v drv_n ...................... 55v vwet ......................... -0.3v to +55v dc driver current per pin ......................... 300ma logic input voltage range ................ -0.3v to vlogic+0.3v discrete input voltage range .................. -80v to +80v continuous power dissipation (ta=+70c) qfn (derate 21.3mw/c above +70c) ........ 1.7w qfp (derate 10.0mw/c above +70c) ........ 1.5w solder temperature (reflow) ........................... 260c junction temperature ............................. 175c storage temperature ............................ -65c to -150c supply voltage vlogic ................................. 3.0v to 5.5v vwet ................................. 7.0v to 36v operating temperature range industrial screening ............. -40c to +85c hi-temp screening ............. -55c to +125c d.c. electrical characteristics vdd = 3.3v or 5v, gnd = 0v, t = operating temperature range (unless otherwise specified). a parameter symbol condition min typ max units discrete inputs sense v+/open sen_sel = high, vwet floating resistance to ground r in 30 k case 1: = gnd ths_sel internal threshold mode open state input voltage v os input voltage to give high output 11.0 v v+ state input voltage v v+ input voltage to give low output 15.5 v input current at 28v i in28 v = 28v in 0.95 ma hysteresis v hy 1.5 v case 2: = open or vlogic ths_sel hi_set/lo_set pin set thresholds hi_set threshold range v hr 0.4 2.2 v lo_set threshold range v lr lo threshold is set to lo_set x 10 0.3 2.1 v min threshold window v thw hi_set > lo_set 0.1 v 10:1 division accuracy as measured by sense output change hi-8425, hi-8426 hi threshold is set to hi_set x 10 v + 0.5 hr v v - 0.5 l r
holt integrated circuits 11 d.c. electrical characteristics (cont) vdd = 3.3v or 5v, gnd = 0v, t = operating temperature range (unless otherwise specified). a logic inputs input voltage v ih input voltage hi 80% vlogic v il input votage lo 20% vlog c i input current, , dsel_n oe i sink v = vlogic, 30k pull down in 125 a i source v = gnd in 0.1 a input current, ths_sel i sink v = vlogic in 0.1 a i source v = gnd , 30k pull up in a input current, snse_sel i sink v = vlogic in 0.1 a i source v = gnd, in 0.1 a 125 parameter symbol condition min typ max units discrete inputs sense gnd/open resistance in series with diode to vlogic r in 3.3 k resistance in series with diode to vwet r w 23.8 k case 1: = gnd ths_sel internal threshold mode ground state input voltage v gs input voltage to give high output 1.0 v open state input voltage v os input voltage to give low output vdd = 5.5v vdd = 3.0v v input current at 0v i in28 v = 0v, vdd = 3.0v v = 0v, vdd = 5.5v in in -0.65 -1.65 ma ma hysteresis v hy 0.15 v case 2: = open or vlogic ths_sel hi_set/lo_set pins set thresholds hi_set threshold range v hr 0.4 2.2 v lo_set threshold range v lr 0.3 2.1 v min threshold window v thw hi_set > lo_set 0.1 v 10:1 division accuracy as measured by sense output change 3.75 2.5 hi-8425, hi-8426 lo threshold is set to lo_set x 10 hi threshold is set to hi_set x 10 v + 0.5 hr v v - 0.5 l r
holt integrated circuits 12 d.c. electrical characteristics (cont) vdd = 3.3v, gnd = 0v, t = operating temperature range (unless otherwise specified). a parameter symbol condition min typ max units analog inputs hi_set/lo_set leakage current i l max leakage for vlogic > v > gnd input -0.1 1.0 a low side drivers on resistance r on i = 200ma see figure 16 source 4.5 8 over current threshold v dcmax maximum v before current limiting. see figure 17 ds 1.5 v over current delay t oc period that driver sinks max current. see figure 17 511 s supply operating vlogic range vlogic 3.0 5.5 v operation vwet range vwet 028v vlogic current i dd1 all sense pins open 10 ma vwet current i vwet all sense inputs = 0v, vwet = 28v 20 ma logic outputs output voltage v oh i = -100 a oh 90% vlog c i v ol i = 100 a ol 10% vlogic output current i ol v = 0.4v out 1.6 ma i oh v = v - 0.4v out logic -1.0 ma tri-state leakage current i tsl v > v > gnd logic out -1.0 1.0 a output capacitance c o 15 pf hi-8425, hi-8426
holt integrated circuits 13 ac electrical characteristics vdd = 3.3v or 5v, gnd = 0v, t = operating temperature range (unless otherwise specified). a parameter symbol condition min typ max units sense v+/open delay, output going high t h1 see figure 13, = gnd, 25 c ths_sel 1.0 s delay, output going low t l1 see figure 13, = gnd, 25 c ths_sel 1.0 s sense gnd/open delay, output going high t h2 see figure 14, = gnd, 25 c ths_sel 1.0 s delay, output going low t l2 see figure 14, = gnd, 25 c ths_sel 1.0 s tri-state delay tri-state delay, on t tson see figure 15, = gnd, 25 c ths_sel 40 ns tri-state delay, off t tsoff see figure 15, = gnd, 25 c ths_sel 40 ns high side drivers turn on delay, dsel_n t son see figure 16, vlogic = 3.3v, 25 c 400 ns turn off delay, dsel_n t soff see figure 16, vlogic = 3.3v, 25 c 900 ns fault output delay, on t fon see figure 17, vlogic = 3.3v, 25 c 15s fault output delay, off t foff see figure 17, vlogic = 3.3v, 25 c 15s hi-8425, hi-8426
holt integrated circuits 14 test circuit and timing diagrams hi-8425, hi-8426 oe so_n 3.3v 3.3v 50% t tson t tsoff so_n vlogic 5k 5k 90% 10% figure 16 low side driver output delay dsel_n drv_n 3.3v 28v 50% t tson t tsoff 90% drv_n 134 100pf 28v 10% dsel_n fault_n 3.3v 3.3v 50% t fon t foff 50% drv_n short to v+ 28v figure 17 low side driver fault delay figure 14 gnd/open output delay figure 15 sense enable output delay sense_n so_n 2.5v gnd 3.3v 1.8v t h2 t l2 so_n 15pf figure 13 28v/open output delay sense_n so_n 28v gnd 3.3v 12v t h1 t l1 so_n 15pf sense_n hi-8425 1.65v t = t = 1s rf t = t = 10ns rf t = t = 10ns rf t = t = 10ns rf t = t = 1s rf
hi - 842xxx x x ordering information holt integrated circuits 15 no -40c to +85c i t f hi-8425, hi-8426 32 - pin plastic quad flat pack (ptqfp) 7mm x 7mm body 32 - vwet 31 - vlogic 30 - hi_set 29 - lo_set 28 - snse_sel 27 - dsel_0 26 - dsel_1 25 - dsel_2 24 - dsel_3 23-drv0 22-drv1 21 - gnd 20 - drv_2 19 - drv_3 18 - fault_or 17 - gnd so_0 - 9 so_1 - 10 so_2 - 11 so_3 - 12 so_4 - 13 so_5 - 14 so_6 - 15 so_7 - 16 sense0 - 1 sense1 - 2 sense2 - 3 sense3 - 4 sense4 - 5 sense5 - 6 sense6 - 7 sense7 - 8 hi-8426pqi hi-8426pqt 44 - pin plastic quad flat pack (pqfp) 10mm x 10mm body 44 - n/c 43 - vlogic 42 - 41 - hi_set 40 - lo_set 39 - snse_sel 38 - fault_or 37 - dsel_0 36 - dsel_1 35 - dsel_2 34 - dsel_3 ths_sel 33 - nc 32 - fault_0 31 - drv_0 30 - drv_1 29 - fault_1 28 - gnd 27 - fault_2 26 - drv_2 25 - drv_3 24 - fault_3 23 - n/c oe - 12 so_0 - 13 so_1 - 14 so_2 - 15 so_3 - 16 so_4 - 17 so_5 - 18 so_6 - 19 so_7 - 20 gnd - 21 n/c - 22 n/c-1 vwet - 2 sense0 - 3 sense1 - 4 sense2 - 5 sense3 - 6 sense4 - 7 sense5 - 8 sense6 - 9 sense7-10 n/c -11 hi-8425pqi hi-8425pqt part number package description 8425pc 40 pin plastic chip scale (40pcs) 8425pq 44 pin plastic quad flat pack (44pmqs) 8426pc 32 pin plastic chip scale (32pcs) 8426pq 32 pin plastic quad flat pack (32pqs) part number temperature range flow burn in i -55c to +125c t no part number lead finish blank tin / lead (sn /pb) solder 100% matte tin (pb-free, rohs compliant)
p/n rev date description of change ds8425 new 12/03/12 initial release a 03/11/13 correct reference to pull-up resistor on inputs from 3.5k to 3.3k. update vwet estimation formulas. clarify vwet value for gnd/open and v+/open sense options in dc characteristics table. update figure 12 input current vs. input voltage charts. delete sensing application table. add more detailed table 2 instead. updated electrical characteristics b 03/25/13 corrected typos in internal threshold limits for v+/open with vwet open. was 11.5v. should be 11.0v. c 08/20/13 updated discrete input voltage range from +/-60v to +/-80v. revision history holt integrated circuits 16 hi-8425, hi-8426
package dimensions holt integrated circuits 17 package type: 40pcs 6.00 .10 6.00 .10 4.1 .05 4.1 .05 0.40 .05 0.25 typ. 0.50 bsc 0.2 typ 0.90 .10 40-pin plastic chip-scale package (qfn) millimeters see detail a detail a 0.02 typ. 0.90 .10 electrically isolated pad on bottom of package. connect to any ground or power plane for optimum thermal dissipation. bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 5.00 .05 (.197 .002) .50 (.020) 32-pin plastic chip-scale package (qfn) millimeters (inches) see detail a detail a .02 typ. (.001 typ.) electrically isolated pad on bottom of package. connect to any ground or power plane for optimum thermal dissipation. package type: 32pcs 5.00 .05 (0.197 .002) .90 .10 (.035 .004) .90 .10 (.035 .004) .25 typ. (.01 typ.) bsc 3.40 .05 (0.134 .002) 3.40 .05 (0.134 .002) bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .40 .05 (.016 .002)
package dimensions holt integrated circuits 18 32 pin plastic quad flat pack (pqfp) inches (millimeters) package type: 32pqs .354 (9.00) bsc sq .047 (1.20) .0315 (0.80) .015 .003 (0.375 .075) .039 .002 (1.0 .05) .003 (.08) .004 .002 (0.10 .05) 0 7 .276 (7.00) bsc sq see detail a detail a .006 .002 (0.14 .06) .024 .006 (0.60 .15) .0057 .002 (0.145 .06) max r min r bsc bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) package type: 0 7 detail a see detail a sq. 44pmqs 44-pin plastic quad flat pack (pqfp) .009 (.23) .520 .010 (13.20 .25) .394 .004 (10.0 .10) sq. max. .014 .003 (.37 .08) .035 .006 (.88 .15) .005 (.13) r min. .012 (.30) r max. .079 .008 (2.0 .20) .096 (2.45) max. .0315 (.80) inches (millimeters) bsc bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95)

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